cs 18: e3

Research Article

Pulse Width Insensitive Design and Verification Methods

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  • @ARTICLE{10.4108/eai.13-7-2018.162635,
        author={Ruchi Shankar and Shalini Eswaran and Sharavathi Bhat and Lakshmanan Balasubramanian},
        title={Pulse Width Insensitive Design and Verification Methods},
        journal={EAI Endorsed Transactions on Cloud Systems: Online First},
        volume={},
        number={},
        publisher={EAI},
        journal_a={CS},
        year={2020},
        month={1},
        keywords={Pulse-width sensitivity, glitch, glitch filter, GLS, SDF, AMS co-simulation, DMS co-simulation, Analog mixed-signal, Digital mixed-signal},
        doi={10.4108/eai.13-7-2018.162635}
    }
    
  • Ruchi Shankar
    Shalini Eswaran
    Sharavathi Bhat
    Lakshmanan Balasubramanian
    Year: 2020
    Pulse Width Insensitive Design and Verification Methods
    CS
    EAI
    DOI: 10.4108/eai.13-7-2018.162635
Ruchi Shankar1,*, Shalini Eswaran1, Sharavathi Bhat2, Lakshmanan Balasubramanian1,*
  • 1: Connected MCU, Texas Instruments (India) Pvt. Ltd., Bengaluru, Karnataka, 560 093, India
  • 2: Analog Technology Development, Texas Instruments (India) Pvt. Ltd., Bengaluru, Karnataka, 560 093, India
*Contact email: r-shankar@ti.com, lakshmanan@ieee.org

Abstract

Many embedded controllers have some critical system states that depend on an asynchronous event. Currently handling them in design depends on the availability of always-on slow clocks. In this paper we present a generic asynchronous design scheme that doesn't require a clock and ensure a reliable functionality without associated deadlock scenarios sensitive to exact arrival times of asynchronous events. This is enabled by a novel pulse width insensitive design method, which also requires unconventional verification methodology that ensures thorough and comprehensive pre-silicon design quality. These have been applied on the latest, ultra-low cost embedded micro-controller design targeted for cost sensitive applications.