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casa 20(20): e5

Research Article

Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications

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  • @ARTICLE{10.4108/eai.12-5-2020.164497,
        author={Cuong Pham-Quoc},
        title={Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications},
        journal={EAI Endorsed Transactions on Context-aware Systems and Applications},
        volume={7},
        number={20},
        publisher={EAI},
        journal_a={CASA},
        year={2020},
        month={5},
        keywords={FPGA-based design framework, Hardware accelerator, Image processing},
        doi={10.4108/eai.12-5-2020.164497}
    }
    
  • Cuong Pham-Quoc
    Year: 2020
    Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications
    CASA
    EAI
    DOI: 10.4108/eai.12-5-2020.164497
Cuong Pham-Quoc1,2,*
  • 1: Ho Chi Minh City University of Technology (HCMUT), 268 Ly Thuong Kiet, District 10, Ho Chi Minh City, Vietnam
  • 2: Vietnam National University – Ho Chi Minh City, Thu Duc District, Ho Chi Minh City, Vietnam
*Contact email: cuongpham@hcmut.edu.vn

Abstract

We present a case study of automatic FPGA-based hardware accelerator design using our proposed framework with the image processing domain. With the framework, the ultimate systems are optimized in both performance and energy consumption. Moreover, using the framework, designers can implement FPGA platforms without manually describing any hardware cores or the interconnect. The systems offer accelerations in execution time compared to traditional general purpose processors and accelerator systems designed manually. We use two applications in the image processing domain as experiments to report our work. Those are Canny edge detection and jpeg converter. The experiments are conducted in both embedded and high-performance computing platforms. Results show that we achieve overall speed-ups by up to 3.15´ and 2.87´ when compared to baseline systems in embedded and high-performance platforms, respectively. Our systems consume less energy than other FPGA-based systems by up to 66.5%.

Keywords
FPGA-based design framework, Hardware accelerator, Image processing
Received
2020-04-10
Accepted
2020-05-10
Published
2020-05-12
Publisher
EAI
http://dx.doi.org/10.4108/eai.12-5-2020.164497

Copyright © 2020 Cuong Pham-Quoc licensed to EAI. This is an open access article distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/3.0/), which permits unlimited use, distribution and reproduction in any medium so long as the original work is properly cited.

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