5th International ICST Conference on Communications and Networking in China

Research Article

A new modeling method for vector processor pipeline using queueing network

Download419 downloads
  • @INPROCEEDINGS{10.4108/chinacom.2010.125,
        author={Tie Qiu and Lei Wang and He Guo and Xiaoyan Liu and Lin Feng and Lei Shu},
        title={A new modeling method for vector processor pipeline using queueing network},
        proceedings={5th International ICST Conference on Communications and Networking in China},
        publisher={IEEE},
        proceedings_a={CHINACOM},
        year={2011},
        month={1},
        keywords={Vector Processor Queueing network Pipeline Modeling Delay},
        doi={10.4108/chinacom.2010.125}
    }
    
  • Tie Qiu
    Lei Wang
    He Guo
    Xiaoyan Liu
    Lin Feng
    Lei Shu
    Year: 2011
    A new modeling method for vector processor pipeline using queueing network
    CHINACOM
    ICST
    DOI: 10.4108/chinacom.2010.125
Tie Qiu1,*, Lei Wang1,*, He Guo1, Xiaoyan Liu1, Lin Feng2,*, Lei Shu3,*
  • 1: School of Software, Dalian University of Technology, Dalian, China, 116620
  • 2: School of Innovation, Experiment, Dalian University of Technology, Dalian, China, 116024
  • 3: Nishio Lab, Osaka University 1-1, Yamadaoka, Suita Osaka, Japan 565-0871
*Contact email: qiutie@dlut.edu.cn, lei.wang@dlut.edu.cn, fenglin@dlut.edu.cn, lei.shu@ieee.org

Abstract

Embedded vector processor is a kind of high-performance parallel processor. Pipeline design is a key technology in embedded vector microprocessors. This paper proposes a new modeling method for vector processor pipeline using open queueing network by instruction set feature of vector processor. According to instruction set distribution of vector processor in the practical projects and owing in the pipeline modeling, the model of pipeline queueing network is analyzed. Total delay and mean delay are computed in every path. A better solution of pipeline is put forward as a result of delay data. Serving time of server nodes is averaged by partitioning for pipeline modeling and adding processing nodes in executing model. In conclusion, the delay data before and after improvement pipeline scheme are analyzed: the delay distributing of improvement scheme is almost equality and choke points with long delay and unequal are avoided.