Area and Power Consumption Estimations at System Level with SystemQ 2.0

Systems-on-Chip (SoC) integrate a complete electronic sys- tem in a single integrated circuit. SoCs typically comprise processors, hardware accelerators, memories, and on-chip in- terconnects. These increasingly complex systems must fulfill many requirements, such as high data throughput, low la- tency, small area, as well as low power consumption and dissipation. In this paper we show how to evaluate an SoC at Elec- tronic System Level (ESL). We use our performance evalu- ation framework SystemQ 2.0 not only to analyze common performance metrics, e. g. throughput, latency, and resource utilization, but also to perform area and power estimations at system level. The foundation of our estimations is a large amount of data from synthesized and physically im- plemented hardware components. From that we build a set of formulas to be integrated into SystemQ. In a case study we show the area and power consump- tion estimations of a complex SoC interconnect. We re- veal how the area and power data are gathered and inte- grated into SystemQ. Based on real test cases we compare the transistor-level data with the system-level results from SystemQ. It will be shown that the error for the area esti- mations is up to 6.3% for single components. The complete system is tested with two standard-cell libraries, whereas the error is 17.0% and 28.1%, respectively. The power estima- tion error is 11.5% at component level.