2nd Internationa ICST Conference on Nano-Networks

Research Article

Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications

  • @INPROCEEDINGS{10.4108/ICST.NANONET2007.2240,
        author={Dimitrios  Tsamados and Yogesh Singh  Chauhan and Christoph  Eggimann and Adrian Mihai  Ionescu},
        title={Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications},
        proceedings={2nd Internationa ICST Conference on Nano-Networks},
        publisher={ACM},
        proceedings_a={NANO-NET},
        year={2010},
        month={5},
        keywords={},
        doi={10.4108/ICST.NANONET2007.2240}
    }
    
  • Dimitrios Tsamados
    Yogesh Singh Chauhan
    Christoph Eggimann
    Adrian Mihai Ionescu
    Year: 2010
    Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications
    NANO-NET
    ICST
    DOI: 10.4108/ICST.NANONET2007.2240
Dimitrios Tsamados1,*, Yogesh Singh Chauhan1, Christoph Eggimann1, Adrian Mihai Ionescu1
  • 1: Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland, CH-1015. Tel.: +41 21 693 39 77, Fax: +41 21 693 36 40
*Contact email: dimitrios.tsamados@epfl.ch

Abstract

Increased interest in hybrid Micro-Electro-Mechanical-Solid-State devices like Suspended-Gate FETs (SGFETs, Fig.1) has been shown recently thanks to their potential for low-power applications, especially as memory cells [1,2]. In principle, the device takes advantage of the movable gate, suspended over the transistor's channel, to obtain very abrupt switching of the FET along with two different voltages for turning the device "on" and "off". Once the gate is at the "up" position the transistor is "off" presenting an extremely low current. Increasing the gate bias VG the gate moves towards the channel and at the "on" voltage it snaps onto the gate oxide driving the SGFET above its threshold providing very high current. The design and the optimization of this kind of device is a considerable challenge due to the lack of dedicated tools for MEMS-Solid-State analysis and numerical simulation. The purpose of this work is to present an original method of coupling state-of-the-art finite element analysis (FEA) tools in a self-consistent way and generate data for SGFET operation. These data are then used for the validation of an analytical model, which is implemented in a circuit simulator to demonstrate the concept of the SGFET as an ultra-low-off-current sleep transistor in advanced CMOS architectures.