A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density

Milos Stanisavljevic; Frank Kagan  Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani

2nd Internationa ICST Conference on Nano-Networks

Research Article

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density

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@INPROCEEDINGS{10.4108/ICST.NANONET2007.2142,
    author={Milos Stanisavljevic and Frank Kagan  G\'{y}rkaynak and Alexandre Schmid and Yusuf Leblebici and Maria Gabrani},
    title={A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density},
    proceedings={2nd Internationa ICST Conference on Nano-Networks},
    proceedings_a={NANO-NET},
    year={2010},
    month={5},
    keywords={Fault-tolerant architecture high defect density reliability of submicron and nanoelectronic systems.},
    doi={10.4108/ICST.NANONET2007.2142}
}

Milos Stanisavljevic
Frank Kagan Gürkaynak
Alexandre Schmid
Yusuf Leblebici
Maria Gabrani
Year: 2010
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density
NANO-NET
ICST
DOI: 10.4108/ICST.NANONET2007.2142

Milos Stanisavljevic¹, Frank Kagan Gürkaynak¹, Alexandre Schmid¹, Yusuf Leblebici¹, Maria Gabrani²

1: Microelectronic Systems Laboratory LSM, Station 11 Swiss Federal Institute of Technology EPFL CH – 1015 Lausanne Switzerland
2: IBM Zurich Research Laboratory Säumerstrasse 4 CH – 8803 Rüschlikon Switzerland

Abstract

This paper presents the development methodology, circuit realization and measurement of a cryptographic core intended to operate reliably in the presence of massive defect density. A circuit-level voter based on averaging and thresholding has been implemented, and is measured to offer superior reliability in comparison with standard techniques.

Keywords: Fault-tolerant architecture high defect density reliability of submicron and nanoelectronic systems.

Published: 2010-05-16
Modified: 2011-09-12

: http://dx.doi.org/10.4108/ICST.NANONET2007.2142

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density

Abstract

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