Research Article
Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications
@INPROCEEDINGS{10.4108/ICST.NANONET2007.2041, author={Fred Chen and Ajay Joshi and Vladimir Stojanović and Anantha Chandrakasan}, title={Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications}, proceedings={2nd Internationa ICST Conference on Nano-Networks}, proceedings_a={NANO-NET}, year={2010}, month={5}, keywords={Carbon nanotube interconnect VLSI on-chip networks.}, doi={10.4108/ICST.NANONET2007.2041} }- Fred Chen
Ajay Joshi
Vladimir Stojanović
Anantha Chandrakasan
Year: 2010
Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications
NANO-NET
ICST
DOI: 10.4108/ICST.NANONET2007.2041
Abstract
The work in this paper addresses the need to evaluate the impact of emerging interconnect technologies, such as carbon nanotubes (CNTs), in the context of system applications. The critical properties of CNTs are described in terms of equivalent material parameters such that a general methodology of interconnect sizing can be used. This methodology is used to rescale the interlayer dielectric (ILD) stack-up and wire dimensions for different combinations of CNT and copper interconnects and vias; the stack-ups are then examined in an on-chip network application. The results of changing the ILD and wire sizing for a conservative estimate assuming a CNT bundle with 1/3 contacted metallic CNTs showed 30% improvement in delay and energy over copper at the 22 nm node and a 50% increase in total system throughput for a power constrained on-chip network application.
