Research Article
Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip
@INPROCEEDINGS{10.4108/ICST.NANONET2007.2035, author={Teijo Lehtonen and Pasi Liljeberg and Juha Plosila}, title={Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip}, proceedings={2nd Internationa ICST Conference on Nano-Networks}, proceedings_a={NANO-NET}, year={2010}, month={5}, keywords={fault tolerance forward error correction nanoscale circuits on-chip communication.}, doi={10.4108/ICST.NANONET2007.2035} }- Teijo Lehtonen
Pasi Liljeberg
Juha Plosila
Year: 2010
Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip
NANO-NET
ICST
DOI: 10.4108/ICST.NANONET2007.2035
Abstract
The amount of errors in future nanoscale technologies is expected to increase dramatically when compared to technologies that have line width larger than 90 nm. In nanoscale CMOS circuits fault tolerance is one of the most important design constraints to sustain system reliability at an acceptable level. We analyze different error correcting coding methods for on-chip communication networks of future nanoscale multiprocessor systems. The implemented communication circuits are compared in terms of error correction capability, circuit area and power consumption. In addition, performance of implemented systems is evaluated under different error scenarios by taking into account variable number of single bit errors, burst errors, and their combinations.