Topology-unaware routing in irregular self-assembled networks-on-chip: an explorative case study

Networks-on-chips (NoCs) offer promising solutions to many of today's on-chip interconnect and communication challenges. While traditional NoC are designed in a top-down way, interconnecting functional blocks with either a regular or a fully customized topology, bottom-up self-assembled conductive nanowires have the potential to create highly complex interconnect fabrics in a very simple way at virtually no cost. However, such complex networks are usually inherently irregular, heterogeneous, and unreliable, and the principal challenge thus consists in developing appropriate paradigms that allow for efficient and reliable communication. Here, we address this challenge on an architectural level within a simple, hybrid, and abstract framework of functional IP blocks that are irregularly interconnected by a nanowire fabric. We have previously shown that certain irregular 3D assemblies and interconnects have major advantages over regular 2D and 3D mesh fabrics in terms of communication performance and the robustness against failures. We extend this body of work and compare the communication properties of simple, local, and topology-unaware routing strategies on several network-on-chip interconnect topologies. We further analyze the scalability and the robustness of these approaches. The results underline the importance of decentralized routing in such assemblies, but also highlight the limits. Our contributions are relevant for the wiring and communication solutions of future bottom-up self-assembled Avogadro-scale systems, and are part of the general effort to explore alternative design paradigms and architectural trade-offs between block granularity and interconnect complexity.