2nd International IEEE/Create-Net Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities

Research Article

Mixed hardware-software testbed for IEEE-802.11n

  • @INPROCEEDINGS{10.1109/TRIDNT.2006.1649185,
        author={Mario  Nicola and Alberto  Dassatti and Guido  Masera and Andrea Concil and Angelo Poloni},
        title={Mixed hardware-software testbed for IEEE-802.11n},
        proceedings={2nd International IEEE/Create-Net Conference on Testbeds and Research Infrastructures for the Development of Networks and Communities},
        publisher={IEEE},
        proceedings_a={TRIDENTCOM},
        year={2006},
        month={7},
        keywords={},
        doi={10.1109/TRIDNT.2006.1649185}
    }
    
  • Mario Nicola
    Alberto Dassatti
    Guido Masera
    Andrea Concil
    Angelo Poloni
    Year: 2006
    Mixed hardware-software testbed for IEEE-802.11n
    TRIDENTCOM
    IEEE
    DOI: 10.1109/TRIDNT.2006.1649185
Mario Nicola1,*, Alberto Dassatti1,*, Guido Masera1,*, Andrea Concil2,*, Angelo Poloni2,*
  • 1: VLSI Lab, Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129 Torino, Italy
  • 2: ST Microelectronics, Via Tolomeo 1, 20010 Cornaredo (Milano) Italy
*Contact email: mario.nicola@polito.it, alberto.dassatti@polito.it, guido.masera@polito.it, andrea.concil@st.com, angelo.poloni@st.com

Abstract

In this paper, the design and implementation of a new high performance hardware channel emulator is presented. The purpose of the developed emulator is to efficiently reproduce in a laboratory environment the accurate behaviour of several effects of the radio channel over a multiple antennas wireless communication system, including AWGN (additive white Gaussian noise), multipath, attenuation and Doppler shift. The main application target is the test and the performance evaluation of a new 802.11n transceiver. The resulting hardware platform is very flexible, allowing, for example, the simulation of systems with variable numbers of input/output antennas, and a programmable number of considered paths as well as their relative delays. The prototype has been implemented on a board including both an ARM processor and a field programmable gate array (FPGA), and it supports the simulation of a 40 MHz radio frequency bandwidth. This paper describes the main issues related with the design of this emulator and reports the laboratory measurements on the first implemented prototype.