Research Article
Chip Design of 10 GHz Low Phase Noise and Small Chip Area PLL
@INPROCEEDINGS{10.1109/ChinaCom.2013.6694605, author={Jhin-Fang Huang and Wen-Cheng Lai and Jiun-Yu Wen and Che-Chi Mao}, title={Chip Design of 10 GHz Low Phase Noise and Small Chip Area PLL}, proceedings={8th International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2013}, month={11}, keywords={pll phase-locked loop phase noise integer-n multi-modulus frequency divider mmfd}, doi={10.1109/ChinaCom.2013.6694605} }- Jhin-Fang Huang
Wen-Cheng Lai
Jiun-Yu Wen
Che-Chi Mao
Year: 2013
Chip Design of 10 GHz Low Phase Noise and Small Chip Area PLL
CHINACOM
IEEE
DOI: 10.1109/ChinaCom.2013.6694605
Abstract
This design describes one of the lowest phase noise an integer-N phase-locked loop (PLL) below 10 GHz offset region using and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a complementary crossed-couple LC-tank voltage- controlled oscillator (VCO) and true single phase clock (TSPC) logic in the frequency divider achieves a tuning range of 1460 MHz from 9.6 to 11.06 GHz with a mixed provide of current mode logic (CML) and according an offset frequency of 1 MHz to obtain lower phase noise performance of -113.47 dBc/Hz from the carry frequency of 10.087 GHz. The locking time is smaller than 3.0 us as simulation. Sum of pads (bonding) and an on-chip third-order low-pass filter, thus makes the chip area occupies only 0.818×0.678 mm2 (0.555 mm2). The power consumption is 39 mW at a supply voltage of 1.8V.
