Research Article
A Low-Power Multi-Bit Delta-Sigma Modulator for Audio Signal Processing
@INPROCEEDINGS{10.1109/CHINACOM.2009.5339880, author={Wan-Rone Liou and Cang-Jhen Lin and Mei-Ling Yeh and Hao-Yuan Siao}, title={A Low-Power Multi-Bit Delta-Sigma Modulator for Audio Signal Processing}, proceedings={ChinaCom2009-Signal Processing for Communications Symposium}, publisher={IEEE}, proceedings_a={CHINACOM2009-SPC}, year={2009}, month={11}, keywords={Dynamic element matching Delta-Sigma Modulator switched capacitor A/D Converte}, doi={10.1109/CHINACOM.2009.5339880} }- Wan-Rone Liou
Cang-Jhen Lin
Mei-Ling Yeh
Hao-Yuan Siao
Year: 2009
A Low-Power Multi-Bit Delta-Sigma Modulator for Audio Signal Processing
CHINACOM2009-SPC
IEEE
DOI: 10.1109/CHINACOM.2009.5339880
Abstract
A low-power high-resolution oversampled 4-bit delta-sigma modulator is designed in this paper. The 2nd-order multi-bit modulator can achieve 14-bit resolution of 24 KHz signal bandwidth when oversampling rate of 128 is used. Fully differential switched capacitor is used to accomplish the modulator. The quantizer is made by a 17-level flash analog-todigital converter. Dynamic element matching technique is used to minimize the capacitor mismatch problem. Data weighted averaging (DWA) can increase SNR by 30 dB when capacitor mismatch is 1% symmetrical linear gradient distribution. SNR improvement with DWA technique is studied on several different capacitor mismatch distribution functions, such as random, linear, and curved distributions. The operational voltage of modulator is 1.8 V, and TSMC 0.25-μm CMOS process is used for the fabrication of this modulator. The modulator with DWA function becomes less sensitive to process variation. The measured SNR of the modulator is 84.3 dB and the power consumption of the modulator is 9.3 mW.