Research Article
An Efficient Hardware Architecture for Deep Packet Inspection in Hybrid Intrusion Detection Systems
@INPROCEEDINGS{10.1109/CHINACOM.2009.5339840, author={Mohammad Amin Taherkhani and Maghsoud Abbaspour}, title={An Efficient Hardware Architecture for Deep Packet Inspection in Hybrid Intrusion Detection Systems}, proceedings={ChinaCom2009-Network and Information Security Symposium}, publisher={IEEE}, proceedings_a={CHINACOM2009-NIS}, year={2009}, month={11}, keywords={}, doi={10.1109/CHINACOM.2009.5339840} }- Mohammad Amin Taherkhani
Maghsoud Abbaspour
Year: 2009
An Efficient Hardware Architecture for Deep Packet Inspection in Hybrid Intrusion Detection Systems
CHINACOM2009-NIS
IEEE
DOI: 10.1109/CHINACOM.2009.5339840
Abstract
Intrusion Detection Systems are known as important security components to establish a protection mechanism for computer and network related resources. By increasing speed of computer networks, and also increasing number of incidents and complexity of attacks; IDSs need to intelligently process the inputs with high performance and precision. A key idea could be an implementation of hardware modules for some components of IDS. In this paper, an efficient hardware architecture is proposed for Network based Intrusion Detection Systems which able to detect known attacks and anomaly behavior over application protocols. Minimum time complexity, low storage cost and improved accuracy and correctness are some key features of the proposed IDS.
