3rd International ICST Conference on Communication and Networking in China

Research Article

A pipelined hardware architecture of deblocking filter in H.264/AVC

  • @INPROCEEDINGS{10.1109/CHINACOM.2008.4685149,
        author={Qing  Chen and Wei Zheng and Jian  Fang and Kai  Luo and Bing Shi and Ming  Zhang and Xianmin Zhang},
        title={A pipelined hardware architecture of deblocking filter in H.264/AVC},
        proceedings={3rd International ICST Conference on Communication and Networking in China},
        publisher={IEEE},
        proceedings_a={CHINACOM},
        year={2008},
        month={11},
        keywords={H.264; deblocking filter; filtering order; pipeline},
        doi={10.1109/CHINACOM.2008.4685149}
    }
    
  • Qing Chen
    Wei Zheng
    Jian Fang
    Kai Luo
    Bing Shi
    Ming Zhang
    Xianmin Zhang
    Year: 2008
    A pipelined hardware architecture of deblocking filter in H.264/AVC
    CHINACOM
    IEEE
    DOI: 10.1109/CHINACOM.2008.4685149
Qing Chen1, Wei Zheng1,2, Jian Fang3, Kai Luo1, Bing Shi1, Ming Zhang1,2, Xianmin Zhang1
  • 1: Institute of Information and Communication Engineering, Zhejiang University, Hangzhou 310027, China
  • 2: Zhejiang Provincial Key Laboratory of Information Network Technology, Hangzhou 310027, China
  • 3: Zhejiang University City College, Zhejiang, Hangzhou 310015, China

Abstract

To improve the performance of in-loop deblocking filter in H.264/AVC, this paper proposes a pipelined hardware architecture. A novel transposer design is presented and its hardware cost is reduced by 15% with forwarding logic to shift pixels. Through adopting a filtering order with vertical and horizontal edges processed alternately, on-chip memory is greatly saved and only two 32times32 bits SRAMs are employed as a buffer. The time to prepare and transfer the intermediate data is also reduced, and only 222 clock cycles are required to filter one macroblock. By processing strong and normal mode filtering simultaneously in a 5-stage pipeline, the proposed architecture can work at a maximum clock frequency of 200 MHz under 0.18 mum technology, and meet the real-time filtering requirement of high-definition (1920times1088) video at a frame rate up to 116 frames per second. Moreover, for applications with low power requirement, it only needs a working frequency of 55 MHz to realize real-time decoding of 1920times1088@30fps video.