Research Article
Lowering the Error Floor of LDPC Codes by a Two-stage Hybrid Decoding Algorithm
@INPROCEEDINGS{10.1109/CHINACOM.2007.4469460, author={Yueguang Bian and Youzheng Wang and Jing Wang}, title={Lowering the Error Floor of LDPC Codes by a Two-stage Hybrid Decoding Algorithm}, proceedings={2nd International ICST Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2008}, month={3}, keywords={AWGN Belief propagation Equations Feedback Geometry Iterative algorithms Iterative decoding Parity check codes Processor scheduling Tin}, doi={10.1109/CHINACOM.2007.4469460} }- Yueguang Bian
Youzheng Wang
Jing Wang
Year: 2008
Lowering the Error Floor of LDPC Codes by a Two-stage Hybrid Decoding Algorithm
CHINACOM
IEEE
DOI: 10.1109/CHINACOM.2007.4469460
Abstract
In this paper, a hybrid decoding scheme is proposed to lower the error floor of low-density parity-check codes. With the observation that some error bits’ LLR values oscillate throughout iterative decoding procedure, a “feedback BP” (FBP) decoding algorithm is presented as second-stage decoding cell to reduce the phenomena of oscillations. The hybrid decoding scheme, which consists LLR-BP decoding algorithm and FBP decoding algorithm, detects errors in the codewords obtained by using the parity check equations of LDPC codes. Simulation results show that the new decoding scheme exhibits a lower error floor than that of belief propagation decoding algorithm in the moderate and high SNR region.
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