Research Article
Testing of Reversible Combinational Circuits
@INPROCEEDINGS{10.1007/978-3-642-35615-5_7, author={Y. Syamala and A. Tilak and K. Srilakshmi}, title={Testing of Reversible Combinational Circuits}, proceedings={Third International conference on advances in communication, network and computing}, proceedings_a={CNC}, year={2012}, month={12}, keywords={Low power design reversible logic fault models testing signature analysis}, doi={10.1007/978-3-642-35615-5_7} }- Y. Syamala
A. Tilak
K. Srilakshmi
Year: 2012
Testing of Reversible Combinational Circuits
CNC
Springer
DOI: 10.1007/978-3-642-35615-5_7
Abstract
Reversible logic is becoming one of the emerging technologies because of its applications in low power design, quantum computing, quantum dot cellular automata and optical computing. As a result, design of reversible logic computing has been gaining more and more attention from researchers, since, under ideal physical circumstances the power dissipation of reversible computing is zero. Conventional decoder and encoder circuits which found applications in memories, processors, communications etc., are power inefficient. In this work, a decoder, encoder and priority encoder are realized using reversible logic to reduce power dissipation. A reversible linear feedback shift register and multiple input signature register are designed to facilitate built – in self-test based on signature analysis. The proposed circuits are tested for single stuck-at, single missing gate and multiple missing gate faults.