Research Article
VLSI Implementation of Burrows Wheeler Transform for Memory Reduced Distributed Arithmetic Architectures
@INPROCEEDINGS{10.1007/978-3-642-35615-5_36, author={Remya A.S. and Lintu Rajan and Shiny C.}, title={VLSI Implementation of Burrows Wheeler Transform for Memory Reduced Distributed Arithmetic Architectures}, proceedings={Third International conference on advances in communication, network and computing}, proceedings_a={CNC}, year={2012}, month={12}, keywords={DWT Burrows Wheeler Transform Distributed Arithmetic Architecture Field programmable gate arrays}, doi={10.1007/978-3-642-35615-5_36} }- Remya A.S.
Lintu Rajan
Shiny C.
Year: 2012
VLSI Implementation of Burrows Wheeler Transform for Memory Reduced Distributed Arithmetic Architectures
CNC
Springer
DOI: 10.1007/978-3-642-35615-5_36
Abstract
Multiply and accumulate function is the important part of digital signal processing algorithms. This can be implemented more effectively with distributed arithmetic (DA) architecture [1]. These architectures make extensive use of look-up tables, which make them ideal for implementing digital signal processing functions on Xilinx FPGAs. An emerging arithmetic-intensive digital signal processing algorithm is the discrete wavelet transform (DWT) which have proven to be extremely useful for image and video coding applications like MPEG-4 and JPEG 2000[2]. But the limitation of this architecture is that the size of look-up tables get increased exponentially as the constant coefficients of wavelet used for these applications increases. In this paper, we proposed a novel methodology to implement the Burrows wheeler transform (BWT) [3] block in FPGA for achieving memory reduced DA.
