Modified Low-Power Multiplier Architecture

Deepthy G.R.; Arathy Iyer; Nishi G.N.

Third International conference on advances in communication, network and computing

Research Article

Modified Low-Power Multiplier Architecture

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@INPROCEEDINGS{10.1007/978-3-642-35615-5_25,
    author={Deepthy G.R. and Arathy Iyer and Nishi G.N.},
    title={Modified Low-Power Multiplier Architecture},
    proceedings={Third International conference on advances in communication, network and computing},
    proceedings_a={CNC},
    year={2012},
    month={12},
    keywords={MODBZ-FAD Bypass register D flip-flop multiplexers Switching activity BZ-FAD architecture power consumption},
    doi={10.1007/978-3-642-35615-5_25}
}

Deepthy G.R.
Arathy Iyer
Nishi G.N.
Year: 2012
Modified Low-Power Multiplier Architecture
CNC
Springer
DOI: 10.1007/978-3-642-35615-5_25

Deepthy G.R.¹, Arathy Iyer², Nishi G.N.³

1: Amritha Vishwavidyapeetham
2: SNGIST Kolencherry
3: Musaliar College of Engineering & Technology

Abstract

In this paper, we have implemented a modified version of the Bypass Zero Feed A Directly (MODBZ-FAD) multiplier architecture based on shift- and add- method. This architecture has considerably low power than the other multiplier architectures. In this architecture we have reduced the power consumption and propagation delay of the circuit. This has been done by removing Bypass register,dflipflop & multiplexers. The synthesis results shows that the switching activity had been lowered up to 78% and power consumption up to 22% when compared up to BZ-FAD architecture.

Keywords: MODBZ-FAD Bypass register D flip-flop multiplexers Switching activity BZ-FAD architecture power consumption

Published: 2012-12-04

: http://dx.doi.org/10.1007/978-3-642-35615-5_25