Research Article
Low Leakage-Power SRAM Cell Design Using CNTFETs at 32nm Technology
@INPROCEEDINGS{10.1007/978-3-642-35615-5_24, author={Rajendra S. and B. Madhavi and K. Kishore}, title={Low Leakage-Power SRAM Cell Design Using CNTFETs at 32nm Technology}, proceedings={Third International conference on advances in communication, network and computing}, proceedings_a={CNC}, year={2012}, month={12}, keywords={SRAM Cell CNTFET Leakage Power HSPICE}, doi={10.1007/978-3-642-35615-5_24} }- Rajendra S.
B. Madhavi
K. Kishore
Year: 2012
Low Leakage-Power SRAM Cell Design Using CNTFETs at 32nm Technology
CNC
Springer
DOI: 10.1007/978-3-642-35615-5_24
Abstract
Leakage power accounts for an increasingly larger portion of total power consumption in nanometer technologies. Battery powered devices remains idle for most of the time except when in use. However, since the phone remains on, it drains power from the battery. This in-turn reduces battery life. In such a situation, battery power can be saved by shutting downthe power supply to the circuit when not in operation. This paper proposes ultra-low power Carbon Nanotube Field-Effect Transistor (CNTFET) based SRAM cell to minimize static power dissipation due to leakage. A Sleep Transistor technique is applied to CNTFET based SRAM cell to reduce leakage power. This method reduces leakage power by dynamically disconnecting supply during inactive state. The 6T SRAM cell circuit using CNTFETs was simulated in HSPICE using Stanford CNFET model at 32nm technology node. The results shows that this method reduces leakage power by 31.5% compared with conventional 6T CNTFET SRAM Cell with minimal area overhead.
