Research Article
High Speed ASIC Design of DCT for Image Compression
@INPROCEEDINGS{10.1007/978-3-642-35615-5_1, author={Deepa Yagain and Ashwini and A. Krishna}, title={High Speed ASIC Design of DCT for Image Compression}, proceedings={Third International conference on advances in communication, network and computing}, proceedings_a={CNC}, year={2012}, month={12}, keywords={Image Compression ASIC Discrete Cosine Transform Vedic Multiplier Pixel}, doi={10.1007/978-3-642-35615-5_1} }- Deepa Yagain
Ashwini
A. Krishna
Year: 2012
High Speed ASIC Design of DCT for Image Compression
CNC
Springer
DOI: 10.1007/978-3-642-35615-5_1
Abstract
This paper gives the design and implementation of an image data compression method such as DCT(Discrete Cosine Transform) using vedic multiplier. This VLSI hardware can be used in practical coding systems to compress images[1]. Discrete cosine transform (DCT) is one of the most popular schemes because of its compression efficiency and small mean square error. DCT is used specially for the compression of images where tolerable degradation is accepted. In this paper, DCT modules are designed, implemented and verified using 90nm technology library using Tanner EDA. Here various individual cores are designed and connected to implement an ASIC for image compression. The Vedic multiplier in this case performs the multiplication much faster when compared to usual array multiplier approach. Due to this, the speed can be increased. Also since all the simulations and implementations are done in 90nm which is one among the deep submicron technologies, the power, area and length of interconnects taken will be less.
