Research Article
CNT Based Channel Interconnect for CMOS Devices
@INPROCEEDINGS{10.1007/978-3-642-27308-7_61, author={Ginto Johnson and Vinod Pangracious}, title={CNT Based Channel Interconnect for CMOS Devices}, proceedings={Advances in Computer Science and Information Technology. Computer Science and Engineering. Second International Conference, CCSIT 2012, Bangalore, India, January 2-4, 2012. Proceedings, Part II}, proceedings_a={CCSIT PATR II}, year={2012}, month={11}, keywords={CNT CNFET HSPICE simulation}, doi={10.1007/978-3-642-27308-7_61} }- Ginto Johnson
Vinod Pangracious
Year: 2012
CNT Based Channel Interconnect for CMOS Devices
CCSIT PATR II
Springer
DOI: 10.1007/978-3-642-27308-7_61
Abstract
MOSFET device dimensions and dimensions of interconnects have been scaled down to increase density, functionality and performance of a chip. Recently, scaling down of dimensions, that has now reached to the nano regime, have led to various issues like electromigration as in the case of interconnects and hot carrier effects, drain induced barrier lowering and so on in case of MOSFET’s. Researchers are thus trying to find other options for interconnects and also new architectures to replace the conventional MOSFET’s. This paper is a study of Carbon Nanotube which is gaining interest of researchers both as device interconnect and channel-interconnect. The behavior of CNT with length and diameter is considered. A study of various parameters like mobility, conductance etc. of the CNT is done. This paper focuses on CNT based FET’s, that are gaining interest as replacements for conventional CMOS, in many modern circuits and also new devices.
