Design and Implementation of Efficient Viterbi Decoders

K. Arunlal; S. Hariprasad

Advances in Computer Science and Information Technology. Computer Science and Engineering. Second International Conference, CCSIT 2012, Bangalore, India, January 2-4, 2012. Proceedings, Part II

Research Article

Design and Implementation of Efficient Viterbi Decoders

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@INPROCEEDINGS{10.1007/978-3-642-27308-7_28,
    author={K. Arunlal and S. Hariprasad},
    title={Design and Implementation of Efficient Viterbi Decoders},
    proceedings={Advances in Computer Science and Information Technology. Computer Science and Engineering. Second International Conference, CCSIT 2012, Bangalore, India, January 2-4, 2012. Proceedings, Part II},
    proceedings_a={CCSIT PATR II},
    year={2012},
    month={11},
    keywords={Constraint length hamming distance path metric branch metric Trellis diagram},
    doi={10.1007/978-3-642-27308-7_28}
}

K. Arunlal
S. Hariprasad
Year: 2012
Design and Implementation of Efficient Viterbi Decoders
CCSIT PATR II
Springer
DOI: 10.1007/978-3-642-27308-7_28

K. Arunlal¹^,*, S. Hariprasad¹

1: R.V. Center for Cognitive Technologies

*Contact email: arunlalks1@yahoo.com

Abstract

Viterbi decoders are used for forward error correction, but the algorithm demands more hardware, memory and computational time, hence researchers have come up with other alternatives like fangled viterbi decoder, modified fangled viterbi decoder, but these methods lack error correction capabilities. In this work an innovative method is used to improve error correction capabilities. The results shows it can correct two bit error with less computational time and hardware requirement.

Keywords: Constraint length hamming distance path metric branch metric Trellis diagram

Published: 2012-11-09

: http://dx.doi.org/10.1007/978-3-642-27308-7_28