Survey on Optimization Techniques in High Level Synthesis

B. Saravanakumaran; M. Joseph

Advances in Computer Science and Information Technology. Computer Science and Engineering. Second International Conference, CCSIT 2012, Bangalore, India, January 2-4, 2012. Proceedings, Part II

Research Article

Survey on Optimization Techniques in High Level Synthesis

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@INPROCEEDINGS{10.1007/978-3-642-27308-7_2,
    author={B. Saravanakumaran and M. Joseph},
    title={Survey on Optimization Techniques in High Level Synthesis},
    proceedings={Advances in Computer Science and Information Technology. Computer Science and Engineering. Second International Conference, CCSIT 2012, Bangalore, India, January 2-4, 2012. Proceedings, Part II},
    proceedings_a={CCSIT PATR II},
    year={2012},
    month={11},
    keywords={High Level Synthesis Very Large Scale Integrated Circuits Functional Units HDL Compiler},
    doi={10.1007/978-3-642-27308-7_2}
}

B. Saravanakumaran
M. Joseph
Year: 2012
Survey on Optimization Techniques in High Level Synthesis
CCSIT PATR II
Springer
DOI: 10.1007/978-3-642-27308-7_2

B. Saravanakumaran¹^,*, M. Joseph²^,*

1: E.G.S. Pillay Engineering College
2: Mother Terasa College of Engineering and Technology

*Contact email: saravanakumaranbalu@yahoo.com, mjoseph_mich@yahoo.com

Abstract

This paper provides a detailed survey of optimization techniques available in high level synthesis. This survey contemplates on two parts. The first part deals with the applicability of optimization techniques available in high level language compiler into high level synthesis. The second part address the topics such as Area optimization, Resource optimization, Power optimization and Optimization issues pertaining to the notions value-grouping, value to register assignment, Transfer to wire assignment and wire to FU port assignment.

Keywords: High Level Synthesis Very Large Scale Integrated Circuits Functional Units HDL Compiler

Published: 2012-11-09

: http://dx.doi.org/10.1007/978-3-642-27308-7_2