Research Article
Qualitative Optimization of Coupling Parasitics and Driver Width in Global VLSI Interconnects
@INPROCEEDINGS{10.1007/978-3-642-27308-7_1, author={Devendra Sharma and Brajesh Kaushik and R. Sharma}, title={Qualitative Optimization of Coupling Parasitics and Driver Width in Global VLSI Interconnects}, proceedings={Advances in Computer Science and Information Technology. Computer Science and Engineering. Second International Conference, CCSIT 2012, Bangalore, India, January 2-4, 2012. Proceedings, Part II}, proceedings_a={CCSIT PATR II}, year={2012}, month={11}, keywords={Delay Crosstalk noise Coupling parasitics Driver width Optimization}, doi={10.1007/978-3-642-27308-7_1} }- Devendra Sharma
Brajesh Kaushik
R. Sharma
Year: 2012
Qualitative Optimization of Coupling Parasitics and Driver Width in Global VLSI Interconnects
CCSIT PATR II
Springer
DOI: 10.1007/978-3-642-27308-7_1
Abstract
Analyses of the effects of interconnect wires in deep sub-micron technology is of prime importance in the modern era integrated circuits. The performance parameters such as crosstalk noise and delay are fundamentally dependent on interconnects and driver sizing. The coupling parasitics are the primary source of crosstalk. This paper addresses the optimization of coupling parasitics and driver sizing qualitatively for delay and peak noise. For this study, a pair of distributed lines each of 4mm length is considered. These lines are coupled inductively and capacitively. The SPICE waveforms are generated at far end of lines for varying coupling parasitics and width of aggressor driver PMOS while keeping channel width of NMOS half of PMOS. The simulation is carried out at 0.13m, 1.5 V technology node. Both the cases of simultaneous switching of inputs in-phase and out-of-phase are taken into consideration.