Towards Brain-inspired Interconnects and Circuits

Research Article

A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations

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  • @INPROCEEDINGS{10.1007/978-3-642-04850-0_36,
        author={Walid Ibrahim and Valeriu Beiu},
        title={A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations},
        proceedings={Towards Brain-inspired Interconnects and Circuits},
        proceedings_a={TBIC},
        year={2012},
        month={5},
        keywords={Reliability Bayesian networks EDA tools nano-circuits},
        doi={10.1007/978-3-642-04850-0_36}
    }
    
  • Walid Ibrahim
    Valeriu Beiu
    Year: 2012
    A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations
    TBIC
    Springer
    DOI: 10.1007/978-3-642-04850-0_36
Walid Ibrahim1,*, Valeriu Beiu1,*
  • 1: UAE University
*Contact email: walidibr@uaeu.ac.ae, vbeiu@uaeu.ac.ae

Abstract

As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nano-circuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design’s overall reliability, and identifying those (few) gates which impact the design’s reliability most significantly.