Towards Brain-inspired Interconnects and Circuits

Research Article

On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations

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  • @INPROCEEDINGS{10.1007/978-3-642-04850-0_33,
        author={Mawahib Sulieman},
        title={On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations},
        proceedings={Towards Brain-inspired Interconnects and Circuits},
        proceedings_a={TBIC},
        year={2012},
        month={5},
        keywords={Reliability threshold voltage CMOS gates},
        doi={10.1007/978-3-642-04850-0_33}
    }
    
  • Mawahib Sulieman
    Year: 2012
    On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations
    TBIC
    Springer
    DOI: 10.1007/978-3-642-04850-0_33
Mawahib Sulieman1,*
  • 1: UAE University
*Contact email: mawahib.sulieman@uaeu.ac.ae

Abstract

This paper discusses the effects of MOSFET threshold voltage variations on the reliability of nanometer-scale CMOS logic gates. The reliability is quantified in terms of the probability-of-failure of individual CMOS gates, which is obtained from extensive Monte Carlo simulations of these gates. The study considers different nano-scale CMOS technology generations and compares the effect of threshold voltage variations on the reliability at the gate level. The results presented here show a clear dependency pattern of reliability on the gate’s input combinations (vectors). The results also show that both the NAND and Majority logic gates can tolerate up to 40% of threshold voltage variations in a 90nm technology, while only up to 20% at the 22nm technology node.