4th International ICST Workshop on Nano-bio-sensing

Research Article

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

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  • @INPROCEEDINGS{10.1007/978-3-642-04850-0_27,
        author={Vinay Saripalli and Vijay Narayanan and Suman Datta},
        title={Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors},
        proceedings={4th International ICST Workshop on Nano-bio-sensing},
        proceedings_a={NANO-BIO-SENSING},
        year={2012},
        month={5},
        keywords={low-energy circuits single electron transistors binary decision diagram logic circuits},
        doi={10.1007/978-3-642-04850-0_27}
    }
    
  • Vinay Saripalli
    Vijay Narayanan
    Suman Datta
    Year: 2012
    Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors
    NANO-BIO-SENSING
    Springer
    DOI: 10.1007/978-3-642-04850-0_27
Vinay Saripalli1,*, Vijay Narayanan1,*, Suman Datta1,*
  • 1: 111 IST Building, The Pennsylvaia State University
*Contact email: vxs924@cse.psu.edu, vijay@cse.psu.edu, sdatta@engr.psu.edu

Abstract

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy – performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.