Nano-Net. 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings

Research Article

Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth

Download
481 downloads
  • @INPROCEEDINGS{10.1007/978-3-642-04850-0_11,
        author={Milos Stanisavljevic and Alexandre Schmid and Yusuf Leblebici},
        title={Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth},
        proceedings={Nano-Net. 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings},
        proceedings_a={NANO-NET},
        year={2012},
        month={5},
        keywords={Fault-tolerance high defect density logic depth redundancy reliability of nanoelectronic systems},
        doi={10.1007/978-3-642-04850-0_11}
    }
    
  • Milos Stanisavljevic
    Alexandre Schmid
    Yusuf Leblebici
    Year: 2012
    Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth
    NANO-NET
    Springer
    DOI: 10.1007/978-3-642-04850-0_11
Milos Stanisavljevic1,*, Alexandre Schmid1,*, Yusuf Leblebici1,*
  • 1: EPFL
*Contact email: milos.stanisavljevic@epfl.ch, alexandre.schmid@epfl.ch, yusuf.leblebici@epfl.ch

Abstract

In this paper we address the possibility to improve the reliability of small to middle-size circuits without employing redundancy. Circuits’ reliability is improved by reducing the logic depth of critical paths since the probability of failure of each output of the circuit depends no the logic depth of critical paths. Circuits of the same size were considered, as well as different synthesized versions of the same circuit and the estimation of the probability of failure is given with respect to the logic depth.