Research Article
A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects
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@INPROCEEDINGS{10.1007/978-3-642-02427-6_15, author={Bo Fu and Paul Ampadu}, title={A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects}, proceedings={Nano-Net. Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers}, proceedings_a={NANO-NET}, year={2012}, month={5}, keywords={Adaptive error control on-chip interconnects hybrid ARQ interleaving}, doi={10.1007/978-3-642-02427-6_15} }- Bo Fu
Paul Ampadu
Year: 2012
A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects
NANO-NET
Springer
DOI: 10.1007/978-3-642-02427-6_15
Abstract
In this paper, we propose a dual-mode hybrid ARQ scheme for energy efficient on-chip communication, where the type of coding scheme can be dynamically selected based on different noise environments and reliability requirements. In order to reduce codec area overhead, a hardware sharing design method is implemented, resulting in only a minor increase in area costs compared to a single-mode system. For a given reliability requirement, the proposed error control scheme yields up to 35% energy improvement compared to previous solutions and up to 18% energy improvement compared to worst-case noise design method.
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