Research Article
A Simplifying Logic Approach for Gate Level Information Flow Tracking
@INPROCEEDINGS{10.1007/978-3-319-78139-6_31, author={Yu Tai and Wei Hu and Dejun Mu and Baolei Mao and Lantian Guo and Maoyuan Qin}, title={A Simplifying Logic Approach for Gate Level Information Flow Tracking}, proceedings={Communications and Networking. 12th International Conference, ChinaCom 2017, Xi’an, China, October 10-12, 2017, Proceedings, Part II}, proceedings_a={CHINACOM}, year={2018}, month={4}, keywords={Hardware security Gate level information flow tracking Security lattice Don’t care Optimization}, doi={10.1007/978-3-319-78139-6_31} }- Yu Tai
Wei Hu
Dejun Mu
Baolei Mao
Lantian Guo
Maoyuan Qin
Year: 2018
A Simplifying Logic Approach for Gate Level Information Flow Tracking
CHINACOM
Springer
DOI: 10.1007/978-3-319-78139-6_31
Abstract
With the increase of design scale and complexity, security vulnerabilities residing in hardware designs become hard to detect. Existing functional testing and verification methods cannot guarantee test and verification coverage in design phase. Fortunately, gate level information flow tracking (GLIFT) has been proposed to enforce bit-tight information flow security from the gate level to detect security vulnerabilities and prevent information leakage effectively. However, there is a significant limitation that the inherent high complexity of GLIFT logic causes significant overheads in static verification and physical implementation. In order to address the limitation, we propose a simplified GLIFT method that incorporates more detailed optimization logic routes to reduce its complexity and allow don’t care to simplify original GLIFT logic. Experimental results have demonstrated that the simplified GLIFT method can reduce the design overhand in several gates by sacrificing a fraction of GLIFT precision.
