Research Article
RSA Encryption Algorithm Design and Verification Based on Verilog HDL
@INPROCEEDINGS{10.1007/978-3-319-73564-1_55, author={Bei Cao and Tianliang Xu and Pengfei Wu}, title={RSA Encryption Algorithm Design and Verification Based on Verilog HDL}, proceedings={Machine Learning and Intelligent Communications. Second International Conference, MLICOM 2017, Weihai, China, August 5-6, 2017, Proceedings, Part I}, proceedings_a={MLICOM}, year={2018}, month={2}, keywords={RSA encryption algorithm Verilog HDL Modular multiplication Montgomery optimization algorithm}, doi={10.1007/978-3-319-73564-1_55} }- Bei Cao
Tianliang Xu
Pengfei Wu
Year: 2018
RSA Encryption Algorithm Design and Verification Based on Verilog HDL
MLICOM
Springer
DOI: 10.1007/978-3-319-73564-1_55
Abstract
Prime number generation and the large number operations directly affect the efficiency of RSA encryption algorithm. In order to reduce the number of the calculation process about modular operation and to reduce the difficulty of division in the calculation process, the Montgomery optimization algorithm is used to carry out the modular multiplication of RSA encryption algorithm, so that the efficiency of the algorithm is improved. Based on the application and research of hardware implementation to information encryption, the Verilog hardware description language is used to design the RSA encryption algorithm in 1024 bits. The simulation results of encryption and decryption experiment show that Montgomery modular multiplication algorithm and RSA encryption algorithm are verified to be correct and effective.
