Research Article
Generation of Low Power SSIC Sequences
@INPROCEEDINGS{10.1007/978-3-319-73447-7_32, author={Bei Cao and Yongsheng Wang}, title={Generation of Low Power SSIC Sequences}, proceedings={Machine Learning and Intelligent Communications. Second International Conference, MLICOM 2017, Weihai, China, August 5-6, 2017, Proceedings, Part II}, proceedings_a={MLICOM}, year={2018}, month={2}, keywords={Single input change sequence BIST Low power testing Fault coverage}, doi={10.1007/978-3-319-73447-7_32} }- Bei Cao
Yongsheng Wang
Year: 2018
Generation of Low Power SSIC Sequences
MLICOM
Springer
DOI: 10.1007/978-3-319-73447-7_32
Abstract
Single input change (SIC) sequence for VLSI testing has been researched because of effectiveness to more test fault models and low power consumption testing. It is the high fault coverage in deterministic built-in self-test (BIST) with low test cost and short test application time. The sequential single input change (SSIC) sequence used in deterministic BIST is presented in this paper for decreasing the dynamic power, reducing test application time and increasing fault coverage. The selection of seed vectors is the significant technique in deterministic BIST. The critical features of SSIC sequence are proposed for selecting seed vectors. The SSIC sequence generator is designed. The simulation results using benchmark circuits show that the SSIC sequences can increase fault coverage and decrease application time than random SIC sequences. SSIC sequence also has low dynamic power consumption.
