Research Article
Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency
@INPROCEEDINGS{10.1007/978-3-319-73423-1_23, author={Harikrishna Parmar and Usha Mehta}, title={Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency}, proceedings={Ubiquitous Communications and Network Computing. First International Conference, UBICNET 2017, Bangalore, India, August 3-5, 2017, Proceedings}, proceedings_a={UBICNET}, year={2018}, month={1}, keywords={Power NoC TAM Test clock frequency Overall test application time (TAT)}, doi={10.1007/978-3-319-73423-1_23} }- Harikrishna Parmar
Usha Mehta
Year: 2018
Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency
UBICNET
Springer
DOI: 10.1007/978-3-319-73423-1_23
Abstract
For a stated core, the test time changes in a staircase pattern with the width of Test Access Mechanism (TAM). The core test time cannot decrease all time with increase in TAM width. However, the test time can always be diminished with increasing the test clock speed but clock speed cannot be increased beyond power limits. Here, a new method is proposed to reduce the Network on Chip (NoC) test time, by differing the test clock frequency such that it doesn’t cross the predefined power limit. The power dissipation, test clock frequency and overall test time is the three trade off. In the proposed method, the clock frequency is optimized to minimize the total test application time (TAT) considering the power limits. Experimental results show an reduction of 48% over existing solution for the benchmark system on chip (SoC) D695, P93791 and P22810.