A Cache Consistency Protocol with Improved Architecture

Qiao Tian; Jingmei Li; Fangyuan Zheng; Shuo Zhao

Advanced Hybrid Information Processing. First International Conference, ADHIP 2017, Harbin, China, July 17–18, 2017, Proceedings

Research Article

A Cache Consistency Protocol with Improved Architecture

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@INPROCEEDINGS{10.1007/978-3-319-73317-3_3,
    author={Qiao Tian and Jingmei Li and Fangyuan Zheng and Shuo Zhao},
    title={A Cache Consistency Protocol with Improved Architecture},
    proceedings={Advanced Hybrid Information Processing. First International Conference, ADHIP 2017, Harbin, China, July 17--18, 2017, Proceedings},
    proceedings_a={ADHIP},
    year={2018},
    month={2},
    keywords={Consistency protocol Multi-core environment Virtual bus},
    doi={10.1007/978-3-319-73317-3_3}
}

Qiao Tian
Jingmei Li
Fangyuan Zheng
Shuo Zhao
Year: 2018
A Cache Consistency Protocol with Improved Architecture
ADHIP
Springer
DOI: 10.1007/978-3-319-73317-3_3

Qiao Tian¹, Jingmei Li¹^,*, Fangyuan Zheng¹, Shuo Zhao¹

1: Harbin Engineering University

*Contact email: lijingmei@hrbeu.edu.cn

Abstract

The effective cache consistency protocol plays an important role in improving the processor performance. This paper designed an improved architecture of consistency protocol for multi-core environment, adding the D-Cache virtual bus to achieve the point-to-point consistency transaction transmission which avoided the bus idle phenomenon caused by the polling query method that the broadcast consistency transaction must be observed. The experimental results show that the architecture can improve the bus utilization.

Keywords: Consistency protocol Multi-core environment Virtual bus

Published: 2018-02-09
Appears in: SpringerLink

: http://dx.doi.org/10.1007/978-3-319-73317-3_3