Wireless Internet. 9th International Conference, WICON 2016, Haikou, China, December 19-20, 2016, Proceedings

Research Article

QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems

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  • @INPROCEEDINGS{10.1007/978-3-319-72998-5_18,
        author={Cang Liu and Chuan Tang and Zuocheng Xing and Luechao Yuan and Yu Wang and Lirui Chen and Yang Zhang and Suncheng Xiang and Wangfeng Zhao and Xing Hu and Jinsong Xu},
        title={QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems},
        proceedings={Wireless Internet. 9th International Conference, WICON 2016, Haikou, China, December 19-20, 2016, Proceedings},
        proceedings_a={WICON},
        year={2018},
        month={1},
        keywords={QRD MU-MIMO MGS ILMGS MILMGS},
        doi={10.1007/978-3-319-72998-5_18}
    }
    
  • Cang Liu
    Chuan Tang
    Zuocheng Xing
    Luechao Yuan
    Yu Wang
    Lirui Chen
    Yang Zhang
    Suncheng Xiang
    Wangfeng Zhao
    Xing Hu
    Jinsong Xu
    Year: 2018
    QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems
    WICON
    Springer
    DOI: 10.1007/978-3-319-72998-5_18
Cang Liu1,*, Chuan Tang1,*, Zuocheng Xing1,*, Luechao Yuan1,*, Yu Wang1,*, Lirui Chen1,*, Yang Zhang1,*, Suncheng Xiang1,*, Wangfeng Zhao1,*, Xing Hu1,*, Jinsong Xu2,*
  • 1: National University of Defense Technology
  • 2: Information Engineering University
*Contact email: liucang@nudt.edu.cn, tc8831@nudt.edu.cn, zcxing@nudt.edu.cn, yuan.luechao@nudt.edu.cn, wangyu16@nudt.edu.cn, chenlirui14@nudt.edu.cn, zhangyang@nudt.edu.cn, xiangsuncheng14@nudt.edu.cn, zhaowangfeng@nudt.edu.cn, 348883881@qq.com, pine_xu@sohu.com

Abstract

QR decomposition (QRD) is one of the performance bottlenecks of transceiver processor in the multiuser multiple-input-multiple-output (MU-MIMO) systems. This paper proposes a QRD algorithm based on the existing modified Gram-Schmidt (MGS) algorithm and iteration look-ahead MGS (ILMGS) algorithm, which is named modified ILMGS (MILMGS) algorithm. A corresponding hardware architecture based on the proposed MILMGS algorithm is designed in 0.13 m CMOS technique to decompose the real matrix. The implementation results show that the gate count of the designed hardware architecture is 250.2 K, the throughput and the critical path are 95.2 M/s and 3.5 ns respectively.