Bit Synchronization and Delayed Decision Feedback Equalization for EDGE BTS - Hardware Implementation on TMS320C6424 TI DSP

Laxmaiah Pulikanti; Pradeep Goutam; Bipsa Purushothaman; K. Dileep; S. Hari Prasad

Wireless and Satellite Systems. 8th International Conference, WiSATS 2016, Cardiff, UK, September 19-20, 2016, Proceedings

Research Article

Bit Synchronization and Delayed Decision Feedback Equalization for EDGE BTS - Hardware Implementation on TMS320C6424 TI DSP

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@INPROCEEDINGS{10.1007/978-3-319-53850-1_9,
    author={Laxmaiah Pulikanti and Pradeep Goutam and Bipsa Purushothaman and K. Dileep and S. Hari Prasad},
    title={Bit Synchronization and Delayed Decision Feedback Equalization for EDGE BTS - Hardware Implementation on TMS320C6424 TI DSP},
    proceedings={Wireless and Satellite Systems. 8th International Conference, WiSATS 2016, Cardiff, UK, September 19-20, 2016, Proceedings},
    proceedings_a={WISATS},
    year={2017},
    month={6},
    keywords={Viterbi equalizer SGRAN BTS The design prototyped in DSP DDFSE MMSE DFE CCS Centre for Development of Telematics (C-DOT)},
    doi={10.1007/978-3-319-53850-1_9}
}

Laxmaiah Pulikanti
Pradeep Goutam
Bipsa Purushothaman
K. Dileep
S. Hari Prasad
Year: 2017
Bit Synchronization and Delayed Decision Feedback Equalization for EDGE BTS - Hardware Implementation on TMS320C6424 TI DSP
WISATS
Springer
DOI: 10.1007/978-3-319-53850-1_9

Laxmaiah Pulikanti¹^,*, Pradeep Goutam¹^,*, Bipsa Purushothaman¹^,*, K. Dileep¹^,*, S. Hari Prasad¹^,*

1: Centre for Development of Telematics

*Contact email: laxman_p@cdot.in, pradeepg@cdot.in, bipsap@cdot.in, dileepkg@cdot.in, svhari@cdot.in

Abstract

This paper demonstrates the implementation of bit synchronization and delayed decision feedback equalization for Enhanced Data rates for GSM Evolution (EDGE) system on TMS320C6424 DSP. EDGE makes use of training sequence for channel estimation and inter symbol interference (ISI) cancellation by use of delayed decision feedback equalization. Modulated baseband in-phase (I) and quadrature (Q) signals are generated using Agilent E4438C Vector signal generator and faded using Agilent fading simulator, is used as input to the DSP. Bit Error Rate (BER) performance of uncoded bits for Packet Data Traffic Channel (PDTCH) meets the EDGE standards. Software implementation uses fixed-point C and Integrated Development Environment (IDE) used for development is code composer studio (CCS). Prototyped our design in Texas Instrument TMS320C6424 DSP and verified for all propagation models as per the EDGE standards. The design and hardware implementation of this Demodulator is done for C-DOT indigenous Shared GSM Radio Access Network (SGRAN) Base Transceiver Station (BTS) project.

Keywords: Viterbi equalizer SGRAN BTS The design prototyped in DSP DDFSE MMSE DFE CCS Centre for Development of Telematics (C-DOT)

Published: 2017-06-05
Appears in: SpringerLink

: http://dx.doi.org/10.1007/978-3-319-53850-1_9