Research Article
A Flexible 5G Receiver Architecture Adapted to VLSI Implementation
@INPROCEEDINGS{10.1007/978-3-319-40352-6_40, author={Vincent Berg and Jean-Baptiste Dor\^{e}}, title={A Flexible 5G Receiver Architecture Adapted to VLSI Implementation}, proceedings={Cognitive Radio Oriented Wireless Networks. 11th International Conference, CROWNCOM 2016, Grenoble, France, May 30 - June 1, 2016, Proceedings}, proceedings_a={CROWNCOM}, year={2016}, month={6}, keywords={FBMC OFDM LTE 5G Architecture}, doi={10.1007/978-3-319-40352-6_40} }- Vincent Berg
Jean-Baptiste Doré
Year: 2016
A Flexible 5G Receiver Architecture Adapted to VLSI Implementation
CROWNCOM
Springer
DOI: 10.1007/978-3-319-40352-6_40
Abstract
A flexible data frame structure adapted to 5G operations and designed to support high bandwidth pipes or sporadic traffic is described. The frame structure imposes to consider receiver architectures that are adapted to orthogonal frequency division mutliplexing (OFDM) for structured synchronous traffic and alternative flexible asynchronous waveforms such as filterbank multicarrier (FBMC) for sporadic traffic. OFDM and FBMC receivers are reviewed and a new flexible receiver architecture is then proposed and described. The design of the new architecture is centered on a memory unit complemented with co-processor units improving the flexibility of the digital signal processing operations of the receiver. The architecture is particularly adapted to application specific integrated circuit. The throughput imposed on the memory and the associated data receiver bus has been evaluated. The evaluation concluded that the throughput is suitable for very large scale integration implementations.
