Research Article
Modeling of Sigma-Delta ADC with High Resolution Decimation Filter
@INPROCEEDINGS{10.1007/978-3-319-11629-7_14, author={G. Sowmya and K. Patel and Rajani Rao}, title={Modeling of Sigma-Delta ADC with High Resolution Decimation Filter}, proceedings={Signal Processing and Information Technology. Second International Joint Conference, SPIT 2012, Dubai, UAE, September 20-21, 2012, Revised Selected Papers}, proceedings_a={SPIT}, year={2014}, month={11}, keywords={Over sampling Noise shaping Decimation filter}, doi={10.1007/978-3-319-11629-7_14} }- G. Sowmya
K. Patel
Rajani Rao
Year: 2014
Modeling of Sigma-Delta ADC with High Resolution Decimation Filter
SPIT
Springer
DOI: 10.1007/978-3-319-11629-7_14
Abstract
This paper presents modeling of Sigma-Delta ADC in time domain and frequency domain. Sigma-Delta converters offer high resolution, high integration, and low cost, making them a good ADC choice for applications such as process control and weighing. Analog block of Sigma-Delta ADC consist of integrator, comparator & feedback loop. Analog block provides one bit stream output, which needs to be decimated by digital filter. The digital part consists of filtering and decimation. Proposed technique uses weighted average method for decimation filter to increase the resolution. To understand the various concepts of Sigma -Delta ADC such as noise shaping, over sampling and digital decimation filtering it is required to build frequency domain model, this makes the analysis simpler. Performance is measured in terms of SNR of decimation filter. Synthesizable Register Transfer Level (RTL) code is written for the decimation filter to verify its performance.