Research Article
A New Nanoscale DG MOSFET Design with Enhanced Performance – A Comparative Study
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@INPROCEEDINGS{10.1007/978-3-319-11629-7_11, author={Sushanta Mohapatra and Kumar Pradhan and Prasanna Sahu}, title={A New Nanoscale DG MOSFET Design with Enhanced Performance -- A Comparative Study}, proceedings={Signal Processing and Information Technology. Second International Joint Conference, SPIT 2012, Dubai, UAE, September 20-21, 2012, Revised Selected Papers}, proceedings_a={SPIT}, year={2014}, month={11}, keywords={MOSFET silicon-on-insulator (SOI) DG SCEs Gate Stack (GS) engineering TM-DG ATLAS device simulator}, doi={10.1007/978-3-319-11629-7_11} }- Sushanta Mohapatra
Kumar Pradhan
Prasanna Sahu
Year: 2014
A New Nanoscale DG MOSFET Design with Enhanced Performance – A Comparative Study
SPIT
Springer
DOI: 10.1007/978-3-319-11629-7_11
Abstract
Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. A lightly doped channel has been taken to enhance the device performance and reduce short channel effects (SCEs) such as drain induced barrier lowering (DIBL), sub threshold slope (SS), hot carrier effects (HCEs), channel length modulation (CLM). We investigated the parameters like Surface Potential, Electric field in the channel, SS, DIBL, Transconductance (g ) for TM-GS-DG and compared with Single Material (SM) DG and TM-DG. The simulation and parameter extraction have been done by using the commercially available device simulation software ATLAS.
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