Research Article
Harnessing Programmable Logic for Quaternion Multiplication
@INPROCEEDINGS{10.1007/978-3-031-84312-9_17, author={Yassen Gorbounov and Hao Chen}, title={Harnessing Programmable Logic for Quaternion Multiplication}, proceedings={Computer Science and Education in Computer Science. 20th EAI International Conference, CSECS 2024, Sofia, Bulgaria, June 28--30, 2024, Proceedings}, proceedings_a={CSECS}, year={2025}, month={3}, keywords={Quaternions Matrix Multiplication Hardware Acceleration FPGA Optimization}, doi={10.1007/978-3-031-84312-9_17} }- Yassen Gorbounov
Hao Chen
Year: 2025
Harnessing Programmable Logic for Quaternion Multiplication
CSECS
Springer
DOI: 10.1007/978-3-031-84312-9_17
Abstract
Quaternions are four-dimensional hyper-complex numbers discovered by Sir William Hamilton in the 19th century. Compared to Euler angles, quaternions allow combining rotations in three-dimensional space and help overcome the problem of not being able to rotate about an axis regardless of rotation about other axes. They find numerous applications in various fields such as mechatronics, computer graphics and signal processing. However, the computational complexity of quaternion multiplication limits its effectiveness in real-time applications. To solve this problem, the paper proposes a hardware-oriented solution based on a programmable logic device (PLD). The design structure is based on the parallel processing and reconfiguration capabilities of the PLD, which can significantly improve the quaternion multiplication performance compared to traditional implementations based on a purely software approach. The paper covers the elaborated multiplier architecture and discusses its advantages in terms of performance and resources used. The experimental work performed highlights the flexibility of the approach used and demonstrates its effectiveness in accelerating quaternion multiplication, making it suitable for real-time applications.
