Research Article
Design and Implementation of Unsigned Serial Divider Using TG Logic
@INPROCEEDINGS{10.1007/978-3-031-81171-5_4, author={G. Kavya and K. Shreshta Reddy and D. Vishnu Prasad and J. V. R. Ravindra and Himanshu Rajeshbhai Dodiya}, title={Design and Implementation of Unsigned Serial Divider Using TG Logic}, proceedings={Broadband Communications, Networks, and Systems. 14th EAI International Conference, BROADNETS 2024, Hyderabad, India, February 16--17, 2024, Proceedings, Part II}, proceedings_a={BROADNETS PART 2}, year={2025}, month={2}, keywords={power consumption high-speed TG logic CMOS}, doi={10.1007/978-3-031-81171-5_4} }- G. Kavya
K. Shreshta Reddy
D. Vishnu Prasad
J. V. R. Ravindra
Himanshu Rajeshbhai Dodiya
Year: 2025
Design and Implementation of Unsigned Serial Divider Using TG Logic
BROADNETS PART 2
Springer
DOI: 10.1007/978-3-031-81171-5_4
Abstract
The paper details the design and implementation of a 4-bit unsigned binary serial divider using 90 nm CMOS technology. It utilizes Transmission Gate (TG) logic for the division process and offers a comparison with an alternative CMOS logic approach featuring a Kogge Stone adder. The TG Logic implementation boasts a lower transistor count (402) but exhibits higher propagation delay (379.6 femtoseconds) and power consumption (18.42 micro-Watts). In contrast, the CMOS Logic with Kogge Stone adder employs more transistors (792) but results in a shorter propagation delay (494.9 femtoseconds) and lower power consumption (5.987 micro-Watts). The choice between these two methods should be based on the specific application’s needs and priorities.
