Research Article
Effective Low Leakage 6T and 8T SRAM Using CMOS 90 nm Technology
@INPROCEEDINGS{10.1007/978-3-031-81171-5_19, author={V. Siddartha Reddy and G. Sumukh and K. Mahesh and P. Kalyani and P. Bindu Swetha}, title={Effective Low Leakage 6T and 8T SRAM Using CMOS 90 nm Technology}, proceedings={Broadband Communications, Networks, and Systems. 14th EAI International Conference, BROADNETS 2024, Hyderabad, India, February 16--17, 2024, Proceedings, Part II}, proceedings_a={BROADNETS PART 2}, year={2025}, month={2}, keywords={Leakage currents CMOS 90 nm Low Power Energy Efficiency Memory design}, doi={10.1007/978-3-031-81171-5_19} }- V. Siddartha Reddy
G. Sumukh
K. Mahesh
P. Kalyani
P. Bindu Swetha
Year: 2025
Effective Low Leakage 6T and 8T SRAM Using CMOS 90 nm Technology
BROADNETS PART 2
Springer
DOI: 10.1007/978-3-031-81171-5_19
Abstract
This study addresses the escalating demand for low-power electronic devices by emphasizing the development of Static Random Access Memory (SRAM) cells with minimized leakage current. The research prioritizes key metrics such as leakage current, read/write stability, access time, and power consumption. To effectively reduce leakage current, reverse-biased FinFETs are employed as efficient switches, creating barriers that impede current flow during idle states. Additionally, power gating techniques selectively disable specific SRAM sub-blocks during inactivity, further reducing static power consumption. This innovative approach, utilizing CMOS 90 nm technology, demonstrates the significance of minimizing leakage current in SRAM cells. The proposed low-leakage 6T and 8T SRAM cells offer a promising solution, contributing to enhanced energy efficiency and performance in memory design. Overall, this research makes notable strides in advancing low-power electronic systems.
