Research Article
Design and Implementing a PCI Express Serdes Block Using HDL
@INPROCEEDINGS{10.1007/978-3-031-81168-5_27, author={Ravali Meesa and G. Surekha}, title={Design and Implementing a PCI Express Serdes Block Using HDL}, proceedings={Broadband Communications, Networks, and Systems. 14th EAI International Conference, BROADNETS 2024, Hyderabad, India, February 16--17, 2024, Proceedings, Part I}, proceedings_a={BROADNETS}, year={2025}, month={2}, keywords={PCI Express Physical layer (PL) Physical Coding Sublayer (PCS) PCI PCIx}, doi={10.1007/978-3-031-81168-5_27} }- Ravali Meesa
G. Surekha
Year: 2025
Design and Implementing a PCI Express Serdes Block Using HDL
BROADNETS
Springer
DOI: 10.1007/978-3-031-81168-5_27
Abstract
This paper introduces a proposal for implementing the Physical Link Layer of PCI Express in accordance with PCI Express 2.0 standards. PCI Express, a high-performance, point-to-point communication protocol, has revolutionized the world of data transfer by offering exceptional bandwidth, making it the go-to choose for a wide array of applications. Its layered architecture, consisting of three distinct layers, facilitates efficient data transfer through packet-based communication between the layers. Widespread use in various applications, including high-speed storage devices, graphics cards, and network cards. The work encompasses the design and verification of multiple physical layer blocks for PCI Express. These blocks are modeled using Verilog at the RTL level and verified using Questasim, a tool from Mentor Graphics.
