Research Article
Implementation and Analysis of PUF Architectures for Enhanced Security
@INPROCEEDINGS{10.1007/978-3-031-81168-5_21, author={Sangeeta Singh and Azmath Noorain and G. Sanjeeva Reddy and Srimanthula Manish Goud}, title={Implementation and Analysis of PUF Architectures for Enhanced Security}, proceedings={Broadband Communications, Networks, and Systems. 14th EAI International Conference, BROADNETS 2024, Hyderabad, India, February 16--17, 2024, Proceedings, Part I}, proceedings_a={BROADNETS}, year={2025}, month={2}, keywords={Physically unclonable functions (PUFs) RO PUF CRO PUF TERO PUF}, doi={10.1007/978-3-031-81168-5_21} }- Sangeeta Singh
Azmath Noorain
G. Sanjeeva Reddy
Srimanthula Manish Goud
Year: 2025
Implementation and Analysis of PUF Architectures for Enhanced Security
BROADNETS
Springer
DOI: 10.1007/978-3-031-81168-5_21
Abstract
Physically Unclonable Functions (PUFs) [Coined in 2001 and 2002] are innovative physical security objects that produce unclonable measurements of physical objects. It acts as an equivalent to the biometrics of human being as it can securely generate and store secrets, PUFs allow advancements in the physical implementation of an information security system. To implement multiple applications, various PUFs were invented using different technologies. Thus, this paper compares and summarizes the characteristics of a set of PUFs using CMOS VLSI technology. The PUF architectures namely RO PUF, CRO PUF, and TERO PUF were designed using Cadence Virtuoso 45 nm technology. It was observed that, when all the constraint parameters were kept the same, according to the implemented sequence, there was a decrease in the usage of memory by 10%. While comparing CRO from RO there is a decrease of 82% in power and 51% in delay, for CRO to TERO there is a 19% decrease in power and a 49% increase in delay as there is a decrease in the number of used transistors.
