Research Article
Design of Single Cycle MIPS RISC Processor Using Re-timing Technique
@INPROCEEDINGS{10.1007/978-3-031-81168-5_17, author={Sindhe Sreeja and Gudipati Sneha and Guguloth Ganesh and Sangeeta Singh}, title={Design of Single Cycle MIPS RISC Processor Using Re-timing Technique}, proceedings={Broadband Communications, Networks, and Systems. 14th EAI International Conference, BROADNETS 2024, Hyderabad, India, February 16--17, 2024, Proceedings, Part I}, proceedings_a={BROADNETS}, year={2025}, month={2}, keywords={MIPS RISC processor Re-timing Pipeline register re-timing}, doi={10.1007/978-3-031-81168-5_17} }- Sindhe Sreeja
Gudipati Sneha
Guguloth Ganesh
Sangeeta Singh
Year: 2025
Design of Single Cycle MIPS RISC Processor Using Re-timing Technique
BROADNETS
Springer
DOI: 10.1007/978-3-031-81168-5_17
Abstract
In designing circuits, the speed and power aspects are crucial. Traditional design faces challenges like increased power use, complex timing issues, and inflexibility in changing certain components. Therefore, there’s a need for new techniques to make designs more efficient. This paper introduces a fresh approach to increase speed of high-speed systems like the MIPS RISC Processor. It does this by combining advanced methods to adjust the timing of signals with flexible strategies for changing certain components. This combination significantly reduces power usage while making the system perform better. Pipeline Register Re-timing Algorithm, strategically adjusts the placement of certain components to reduce delays in signal movement and the time it takes for the system clock to complete a cycle. This results in an overall improvement in how well the system performs. The design is implemented practically using the Xilinx Vivado tool with the Verilog High Descriptive Language (VHDL). The outcomes of this implementation show a clear reduction in critical path and delay, along with more efficient power usage. This study reveals a 2% decrease in total On Chip power, a 2% reduction in dynamic power, and a 2.5% decline in input signal power.
