Research Article
Low Power VLSI Architecture for Rail To Rail Dynamic Voltage Comparator
@INPROCEEDINGS{10.1007/978-3-031-81168-5_11, author={S. Karunakaran and S. Srivardhan and M. Harshith and K. SaiManish}, title={Low Power VLSI Architecture for Rail To Rail Dynamic Voltage Comparator}, proceedings={Broadband Communications, Networks, and Systems. 14th EAI International Conference, BROADNETS 2024, Hyderabad, India, February 16--17, 2024, Proceedings, Part I}, proceedings_a={BROADNETS}, year={2025}, month={2}, keywords={Dynamic comparator low voltage RR-DVC CMOS low power PUN-Pull Up Network PDN-Pull Down network VGS-Gate to Source Voltage Cadence Virtuoso}, doi={10.1007/978-3-031-81168-5_11} }- S. Karunakaran
S. Srivardhan
M. Harshith
K. SaiManish
Year: 2025
Low Power VLSI Architecture for Rail To Rail Dynamic Voltage Comparator
BROADNETS
Springer
DOI: 10.1007/978-3-031-81168-5_11
Abstract
Rail to Rail Dynamic Voltage Comparator (RRDVC) works on very low voltages which is constructed and developed using cadence virtuoso tool. Here 90nm technology was used to construct and analyse the 3 different architectures of Rail to Rail Dynamic Voltage Comparators.Here Three different architectures are made by varying the stages with NOT of AND and NOT of OR. The power dissipation, delay and the power delay products(PDP) are compared for the three different architectures developed by varying the inputs. Comparator circuit takes the analog signal , reference voltage and the clock signal as input and gives the outputs as digital signals with 0’s and 1’s. not operation of AND and not operation of OR based stages are arranged as per requirement to obtain the three different architectures and the outputs of these stages are combined using latch circuits. The outputs are obtained for different frequencies of input analog signals with the different reference voltage. All these architectures are implemented using basic CMOS transistors. The power dissipations obtained here are(1.9 \times {10^{-6}})W ,(19 \times 10^{-12})W and(1.7 \times 10^{-6})W for the RRDVC with NOT of AND and OR , NOT of NAND, and NOT of OR based stages respectively. The architecture with NOT of AND stages provides less power when compared to the other architectures.
