Research Article
Design of 8-bit 2 GHz Current-Steering DAC
@INPROCEEDINGS{10.1007/978-3-031-60347-1_1, author={Haoyi Li}, title={Design of 8-bit 2 GHz Current-Steering DAC}, proceedings={Mobile Multimedia Communications. 16th EAI International Conference, MobiMedia 2023, Guilin, China, July 22-24, 2023, Proceedings}, proceedings_a={MOBIMEDIA}, year={2024}, month={10}, keywords={Digital-to-analog (DAC) CMOS Current-steering}, doi={10.1007/978-3-031-60347-1_1} }- Haoyi Li
Year: 2024
Design of 8-bit 2 GHz Current-Steering DAC
MOBIMEDIA
Springer
DOI: 10.1007/978-3-031-60347-1_1
Abstract
In this paper, an 8-bit 2 GHz current steering DAC based on SMIC 55 nm CMOS process is designed. The design is mainly divided into two parts: analog part and digital part. The analog part contains a bandgap reference voltage source providing a small temperature coefficient reference voltage, a bias voltage generation circuit and a current source consisting of a cascode current mirror, while the digital part mainly contains an input register, a dual 4-bit thermometer decoder and a switch driver. After the digital signal is input, it is first synchronized by the clock drive register and uniformly input into the high and low thermometer decoders, and then the switch driver module translates the decoded signal into a high cross-point drive signal to ensure that the NMOS switches of the current source do not turn off simultaneously, ensuring the accuracy and stability of the output signal.
By improving the structure of the low-voltage cascode current mirror, the DAC obtains better output stability at low voltage. The overall simulation of DAC using EDA tool shows that the start-up time of DAC is less than 0.5 ns under the pre-simulation condition of 27 ℃, and the DNL is 0.375 LSB and INL is 0.492 LSB at 2 GHz sampling frequency, which proves that DAC has good working ability at this frequency.
