Research Article
Area Efficient and Ultra Low Power Full Adder Design Based on GDI Technique for Computing Systems
@INPROCEEDINGS{10.1007/978-3-031-48891-7_5, author={T. Saran Kumar and I. Rama Satya Nageswara Rao and Y. Satya Vinod and P. Harika and B. V. V. Satyanarayana and A. Pravin}, title={Area Efficient and Ultra Low Power Full Adder Design Based on GDI Technique for Computing Systems}, proceedings={Cognitive Computing and Cyber Physical Systems. 4th EAI International Conference, IC4S 2023, Bhimavaram, Andhra Pradesh, India, August 4-6, 2023, Proceedings, Part II}, proceedings_a={IC4S PART 2}, year={2024}, month={1}, keywords={MVT GDI ULV TGA TFA Energy Delay Product}, doi={10.1007/978-3-031-48891-7_5} }- T. Saran Kumar
I. Rama Satya Nageswara Rao
Y. Satya Vinod
P. Harika
B. V. V. Satyanarayana
A. Pravin
Year: 2024
Area Efficient and Ultra Low Power Full Adder Design Based on GDI Technique for Computing Systems
IC4S PART 2
Springer
DOI: 10.1007/978-3-031-48891-7_5
Abstract
The relevance of ultra-low-voltage (ULV) operation for attaining minimal energy usage has increased recently. The fundamental building element of computational arithmetic in many computer and signal/image processing applications is the full adder. An innovative 1-bit hybrid adder circuit that uses both multi-threshold voltage (MVT) transistor logic and GDI (gate-diffusion input) logic is disclosed. The suggested motivation of the Multi Threshold Voltage-gate-diffusion input hybrid adder design is to furnish low energy efficient utilization with a small footprint. Standard 45 nano-meter CMOS process technology is used to simulate the suggested hybrid architecture with a ULV of 0.2 V. The suggested design made considerable improvements in contrast to the previous published designs, yielding >57% and 92% reductions Using only 14 transistors in the Energy and Delay Product respectively, according to the post-layout simulation findings. The suggested design technique produces full functionality, which shows resistance against the processes of global, local variations. The suggested design offers >57% energy efficient compared to the current efforts, according to energy measures that are adjusted for 32 and 22 nm technologies.
