Research Article
LUT-Based Area-Optimized Accurate Multiplier Design for Signal Processing Applications
@INPROCEEDINGS{10.1007/978-3-031-48888-7_26, author={B. V. V. Satyanarayana and B. Kanaka Sri Lakshmi and G. Prasanna Kumar and K. Srinivas}, title={LUT-Based Area-Optimized Accurate Multiplier Design for Signal Processing Applications}, proceedings={Cognitive Computing and Cyber Physical Systems. 4th EAI International Conference, IC4S 2023, Bhimavaram, Andhra Pradesh, India, August 4-6, 2023, Proceedings, Part I}, proceedings_a={IC4S}, year={2024}, month={1}, keywords={Multiplier FPGA LUT Power vertex 7}, doi={10.1007/978-3-031-48888-7_26} }- B. V. V. Satyanarayana
B. Kanaka Sri Lakshmi
G. Prasanna Kumar
K. Srinivas
Year: 2024
LUT-Based Area-Optimized Accurate Multiplier Design for Signal Processing Applications
IC4S
Springer
DOI: 10.1007/978-3-031-48888-7_26
Abstract
Multipliers play a role in various aspects of smart cities, which can be used in many applications like Traffic management, energy management and environmental management etc. The wide variety of applications of multipliers are in the field of signal processing and image processing. FPGA design of multiplier is one of the complex tasks in Digital electronics. Most of the designs uses DSP blocks, these multipliers are complex and occupies much area in FPGA. Accurate multiplier design with low area on FPGA is the challenging task. The proposed method is accurate multiplier design, which is designed only using lookup table (LUT). The proposed design has low power and reduced area because of using simple LUT’s for generating partial product. The proposed accurate multipliers reduce 10% less Hardware on vertex 7 FPGA compared to existing designs.
