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IoT as a Service. 8th EAI International Conference, IoTaaS 2022, Virtual Event, November 17-18, 2022, Proceedings

Research Article

A Resource- and Power-Efficient Implementation of PSS Synchronization on FPGA in Vehicular Networks

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BibTeX Plain Text
  • @INPROCEEDINGS{10.1007/978-3-031-37139-4_13,
        author={Chengxiang Ge and Fei Peng and Shan Cao and Zhiyuan Jiang and Terng-Yin Hsu},
        title={A Resource- and Power-Efficient Implementation of PSS Synchronization on FPGA in Vehicular Networks},
        proceedings={IoT as a Service. 8th EAI International Conference, IoTaaS 2022, Virtual Event, November 17-18, 2022, Proceedings},
        proceedings_a={IOTAAS},
        year={2023},
        month={7},
        keywords={Synchronization FPGA Primary Synchronization Signal(PSS)},
        doi={10.1007/978-3-031-37139-4_13}
    }
    
  • Chengxiang Ge
    Fei Peng
    Shan Cao
    Zhiyuan Jiang
    Terng-Yin Hsu
    Year: 2023
    A Resource- and Power-Efficient Implementation of PSS Synchronization on FPGA in Vehicular Networks
    IOTAAS
    Springer
    DOI: 10.1007/978-3-031-37139-4_13
Chengxiang Ge1, Fei Peng1, Shan Cao1, Zhiyuan Jiang1,*, Terng-Yin Hsu2
  • 1: School of Communication and Information Engineering, Shanghai University
  • 2: Department of Computer Science
*Contact email: jiangzhiyuan@shu.edu.cn

Abstract

This paper proposes a resource- and power-efficient implementation of primary synchronization signal (PSS) synchronization on FPGA in vehicular networks. Firstly, the received signal is preprocessed. Secondly, the synchronization signal is detected and its timing position is calculated. Thirdly, a sequence is extracted for frequency offset estimation. Finally, the received original signal is marked with the frame header and compensated with proper frequency offset. The hardware implementation scheme is based on FPGA and uses the advantages of FPGA high-speed pipeline computing to realize real-time sampling and synchronization of transmitter and receiver, the consumption of Slice Look-Up-Table (LUT) is 9545 and the total on-chip power is 1.213 w.

Keywords
Synchronization FPGA Primary Synchronization Signal(PSS)
Published
2023-07-19
Appears in
SpringerLink
http://dx.doi.org/10.1007/978-3-031-37139-4_13
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